1. Field of the Invention
This invention relates to a moving picture decoding device for reading picture data from a picture memory responsive to a motion vector for decoding the moving picture.
2. Description of the Related Art
There are a variety of systems for compressing and encoding moving picture signals, such as television telephone or television conference signals or telecast signals. Recently, a hybrid encoding system, such as MC-DCT, which consists in a combination of a so-called motion compensated (MC) inter-frame prediction and discrete cosine transform (DCT), is thought to be promising.
FIG. 1 shows a circuit for an encoding device conforming to the above-mentioned MC-DCT hybrid system. In this figure, moving picture signals, such as television signals, are supplied as input signals to an input terminal 111. These input signals are supplied to a motion detection circuit 113 and a subtractive node 114 via a picture memory 112 employed as a frame memory. An output of the subtractive node 114 is transmitted to a DCT circuit 115 for discrete cosine transformation and thence supplied to a quantizer 116 for quantization before being supplied to a series circuit consisting of a inverse quantization unit 117 and an inverse DCT (IDCT) circuit 118 as a local decoder. An output of the IDCT circuit 118 is supplied via an additive node 119 to a picture memory 120 employed as a frame memory. An output read from the picture memorv 120 is transmitted to the motion detection circuit 113 and to a motion compensation circuit 121. The motion detection information such as the motion vector from the motion detection circuit 113 is transmitted to the motion compensation circuit 121 and to a variable length coding circuit 123. An output of the motion compensation circuit 121 is supplied to the subtractive node 114 and to the additive node 119.
It is noted that the input signals are stored temporarily in the picture memory 112 and subsequently read out and processed on the basis of a block of a pre-set size. The motion detection circuit 113 compares the values of pixels of a signal block from the picture memory 112 to the values of pixels of locally decoded signals from the picture memory 120 for detecting the motion vector. The motion compensation circuit 121 outputs a reference block to the subtractive node 114 based on this motion vector. The subtractive node 114 outputs a difference between the input signal block and the reference block. The difference output is discrete cosine transformed by the DCT circuit 115 and quantized by the quantizer 116 before being supplied to the variable length coding unit 123 such as an entropy coding unit for variable length coding. The motion vector from the motion detection circuit 113 is also supplied to the variable length coding unit 123.
An output of the variable length coding unit 123 is supplied to a transmitting buffer memory 125 where the coded data to be transmitted is stored transiently. These coded data are supplied to the quantizer 116 and to the variable length coding unit 123. In this manner, the operation of quantization and variable length coding is carried out by the quantizer 116 and the variable length coding unit 123 so that the amount of transmitted data per unit time will be constant. The coded data, which is caused to be transmitted in a constant quantity per unit time, is transmitted over a communication network via an output terminal 126 or recorded or reproduced on or from a recording medium.
In decoding the signals, processed with the above-described MC-DCT hybrid coding operations, by the local decoder within the encoder or within the moving picture device, it is necessary to read out data of a frame directly preceding the current frame from the frame memory depending on the motion vector to perform motion compensation thereon.
The frame memory is made up of a number of memory elements, such as DRAMs, and is adapted for reading out data from the memory elements by parallel reading with four bytes, as an example, as a word, at a rate of one byte from each memory element. Consequently, in decoding the signals coded in accordance with the above-described MC-DCT hybrid coding, by way of picture decoding, it is necessary to have a high-speed access to the frame memory.
However, if a DRAM shown in FIG. 2, in which access to the data is had by row and column addresses, is employed as a frame memory, it has been impossible to read out data continuously.
An illustrative method for reading out data from this DRAM is explained with reference to a timing chart of FIG. 3. In this figure, "CLK" denotes clock pulses. "/CS" denotes a logical signal to be supplied to an L-active chip select terminal and its timing. "/RAS" denotes a logical signal to be supplied to a random access terminal for a row which is L-active and its timing. "/CAS" denotes a logical signal to be supplied to a random access terminal for a column which is L-active. "/WE" (not shown in FIG. 3) denotes aolgical signal to be supplied to a write enable terminal which is L-active and its timing. "Add" denotes the state of the setting line for the row and column addresses. "Out" denotes a readout data output. More precisely, the logical signal of chip select (CS) is L-active, so that it is expressed as "/CS". Similarly, the row and column addresses are also L-active, so that they are expressed as "/RAS" and "/CAS", respectively. The logical signal of write enable is also L-active, so that it is expressed as "/WE". The setting line for the row and column addresses is "Add". The readout data output is "Out". When an L-level logical signal is applied as "/CS" and "/RAS", and an H-level logical signal is supplied as "/CAS", "Add" is set to a row address R.sub.0. When an L-level logical signal is applied as the logical signals "/CS" and "/CAS", and an H-level logical signal is supplied to "/RAS", "Add" is set to a column address C.sub.o. Data D.sub.00, D.sub.10 . . . , D.sub.70 are then outputted as "Out" after the third clock after the setting of the column address C.sub.0.
After outputting of a data D.sub.70, an L-level logic signal is again applied to the terminals "/CS" and "/RAS", and an H-level logic signal is applied to the terminal "/CAS". At this time, the state "Add" is set to a row address R.sub.1. Then, an L-level logic signal is applied to each of the terminals "/CS" and "/RAS", and an H-level logic signal is applied to the terminal "/RAS". At this time, the state "Add" is set to a column address C.sub.1. Then, after the third clock after such setting of C.sub.1, data D.sub.01, D.sub.11, D.sub.21, . . . are outputted as "Out".
That is, if the DRAM is employed as the picture memory as described above, it becomes necessary to set the row address each time the row is changed, such that continuous data reading is not possible, that is data D.sub.01 cannot be outputted after data D.sub.70 without setting a time interval corresponding to five clocks.